1. Any signed negative binary number is recognised by its nibble msb byte lsb 2. The way to speed up DTL is to add an across intermediate resister is small speed-up capacitor small speed-up transistor large speed-up capacitor large speed-up transistor 3. An important drawback of binary system is it requires large string of 1s and small string of 0s to represent a decimal number it requires very large string of 1s and 0s to represent a decimal number it requires small string of 1s and large string of 0s to represent a decimal number it requires sparingly small string of 1s and 0s to represent a decimal number 4. The full form of CTDL is complementary transistor diode logic complementary transistor direct logic complemented transistor direct logic complemented transistor diode logic 5. Compatibility refers to the input of a circuit should match with the output of same circuit the input of a circuit should match with the output of another circuit the output of a circuit should match with the input of another circuit the output of a circuit should match with the input of the same circuit 6. The DTL propagation delay is relatively negligible small large moderate 7. A major advantage of DTL over the earlier resistor-transistor logic is the increased fan out decreased fan in decreased fan out increased fan in 8. A disadvantage of DTL is the increased fan-in the input resister to the transistor the increased fan-out the input transistor to the resister 9. Which of the following tool performs logic optimization? rtl compiler synthesis tool simulation tool routing tool 10. The first CML logic was introduced by General Electric in 1990 1960 1981 1961 11. The decimal equivalent of the octal number (645)8 is (451)10 (450)10 (501)10 (421)10 12. The quantity of double word is 16 bits 8 bits 32 bits 4 bits 13. To increase fan-out of the gate in DTL an additional transistor and diode may be used only an additional diode may be used an additional resister may be used an additional capacitor may be used 14. Which flip-flop is usually used in the implementation of the registers? s-r flip-flop t flip-flop j-k flip-flop d flip-flop 15. The process to avoid saturating the switching transistor is performed by baker clamp chris brown james r. biard totem-pole 16. What does RTL in digital circuit design stand for? register transfer logic register transfer level register transfer language resistor-transistor logic 17. RTL is used in HDL to create what level of representations in the circuit? same level mid-level high-level low-level 18. All input of NOR as low produces result as. low floating high mid 19. RTL mainly focuses on describing the flow of signals between logic gates inverter clock registers 20. Hold time is the time needed for the data to after the edge of the clock is triggered. negate remain constant decrease increase 21. The method of connecting a driving device to a loading device is known as sourcing compatibility sinking interface 22. RTL is a design abstraction of what kind of circuit? synchronous digital circuit analog circuit asynchronous digital circuit asynchronous sequential circuit 23. Simulator enters in which phase after the initialization phase? simulation phase execution phase elaboration phase compilation phase 24. The largest two digit hexadecimal number is (fd)16 (ef)16 (ff)16 (fe)16 25. Schottky families prevent the saturating using transistors diodes schottky diodes schottky transistors 26. All input of NOR as low produces result as low high impedance mid high 27. Motorola has offered MECL circuits in logic families. 3 5 4 6 28. In RTL NOR gate, the output is at logic 1 only when all the inputs are at logic 0 floating +10v logic 1 29. Why latches are called a memory devices? it can store one bit of data it has internal memory of 4 bit it can store infinite amount of data it has capability to stare 8 bits of data 30. The full form of CMOS is complemented metal oxide semiconductor capacitive metallic oxide semiconductor complementary metal oxide semiconductor capacitive metal oxide semiconductor 31. Whose operations are more faster among the following? flip-flops latches sequential circuits combinational circuits 32. The full form of MECL is motorola emitter capacitor logic motorola emitter coupled logic mono emitter coupled logic both mono emitter and motorola coupled logic 33. The output of latches will remain in set/reset untill they dont get any pulse more the trigger pulse is given to change the state any pulse given to go into previous state the pulse is edge-triggered 34. The basic idea of basic CML circuit came from an both inverter and buffer buffer inverter transistor 35. How many types of sequential circuits are? 2 4 5 3 36. The latest entrant to the ECL family is ecl 100k ecl 1000k ecl 10k ecl 10000k 37. The basic latch consists of two adders two comparators two amplifiers two inverters 38. In S-R flip-flop, if Q = 0 the output is said to be previous state reset current state set 39. What is a trigger pulse? a pulse that reverses the cycle of operation a pulse that starts a cycle of operation a pulse that enhances a cycle of operation a pulse that prevents a cycle of operation 40. A latch is an example of a 555 timer bistable multivibrator astable multivibrator monostable multivibrator 41. CMOS is also sometimes referred to as complemented symmetry metal oxide semiconductor complementary symmetry metal oxide semiconductor capacitive metal oxide semiconductor capacitive symmetry metal oxide semiconductor 42. Latch is a device with two stable state three stable state infinite stable states one stable state 43. How many types of latches are __ 3 2 4 5 44. The full form of COS-MOS is complementary systematic metal oxide semiconductor complemented systematic metal oxide semiconductor capacitive symmetry metal oxide semiconductor complementary symmetry metal oxide semiconductor 45. The sequential circuit is also called adder latch strobe flip-flop 46. Two stable states of latches are astable & monostable low output & high input high output & low output low input & high output 47. CMOS technology is used in microprocessor digital logic both microprocessor and digital logic inverter 48. The first step of analysis procedure of SR latch is to label outputs label inputs label tables label states 49. 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