JEE Physics Semiconductor Electronics MCQs Set 07

Multiple Choice Questions (MCQs) for JEE Physics: Semiconductor Electronics

Access targeted multiple-choice questions for Semiconductor Electronics designed to align with the latest JEE academic syllabus for JEE Physics. These objective practice sets help students evaluate their conceptual understanding and improve exam readiness.

Practice Semiconductor Electronics MCQs for JEE Physics

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Multiple Choice Questions

Question 1: In an n-p-n transistor amplifier in common emitter configuration, the current gain is 100. If the collector current changes by 1 mA, the change in emitter current is:
(a) 1.1 mA
(b) 1.01 mA
(c) 0.01 mA
(d) 10 mA
Show Answer & Explanation

Answer: (b) 1.01 mA

Explanation:
1. \( \Delta I_B = \Delta I_C/\beta = 0.01 \) mA.
2. \( \Delta I_E = \Delta I_C + \Delta I_B = 1.01 \) mA.

Teacher's Note:
1. Emitter current is the sum of collector and base currents.

Question 2: A two-input XOR gate produces a high output only when its inputs are:
(a) the same
(b) different
(c) low
(d) high
Show Answer & Explanation

Answer: (b) different

Explanation:
1. XOR output is 1 if the inputs differ.
2. It is 0 when they are equal.

Teacher's Note:
1. XOR: Y = A·B̄ + Ā·B.

Question 3: In Boolean algebra, which of the following is not equal to zero?
(a) \( A \cdot \bar{A} \)
(b) \( A \cdot 0 \)
(c) \( \overline{A + \bar{A}} \)
(d) \( \overline{A \cdot 0} \)
Show Answer & Explanation

Answer: (d) \( \overline{A \cdot 0} \)

Explanation:
1. \( A\bar{A} = 0 \) and \( A \cdot 0 = 0 \).
2. \( A + \bar{A} = 1 \), so its complement is 0.
3. \( \overline{A \cdot 0} = \bar{0} = 1 \).

Teacher's Note:
1. Simplify inside the bar first.

Question 4: Digital circuits can be made by repetitive use of:
(a) OR gate
(b) AND gate
(c) NOT gate
(d) NAND gate
Show Answer & Explanation

Answer: (d) NAND gate

Explanation:
1. NAND and NOR are universal gates.
2. Any logic function can be built from NAND gates alone.

Teacher's Note:
1. Universal gates: NAND and NOR.

Question 5: When all the inputs of a NAND gate are connected together, the resulting circuit is:
(a) a NOT gate
(b) an AND gate
(c) an OR gate
(d) a NOR gate
Show Answer & Explanation

Answer: (a) a NOT gate

Explanation:
1. \( Y = \overline{A \cdot A} = \bar{A} \).
2. This is a NOT gate.

Teacher's Note:
1. This is one way of making an inverter from NAND.

Question 6: A NAND gate followed by a NOT gate is:
(a) an OR gate
(b) an AND gate
(c) a NOR gate
(d) a XOR gate
Show Answer & Explanation

Answer: (b) an AND gate

Explanation:
1. NAND gives \( \overline{AB} \).
2. Inverting it gives AB, which is AND.

Teacher's Note:
1. NAND = AND followed by NOT.

Question 7: The NOR gate is logically equivalent to an OR gate followed by:
(a) an inverter
(b) a NOR gate
(c) a NAND gate
(d) an AND gate
Show Answer & Explanation

Answer: (a) an inverter

Explanation:
1. NOR output is \( \overline{A+B} \), which is OR followed by NOT.
2. No other option gives this.

Teacher's Note:
1. NOR = OR + NOT.

Question 8: An OR gate with inputs A and B has its output connected to one input of an AND gate; input A also goes directly to the other input of the AND gate. The output Y equals:
(a) A
(b) \( \bar{A} \)
(c) A + B
(d) AB
Show Answer & Explanation

Answer: (a) A

Explanation:
1. \( Y = A (A+B) = A + AB = A \).

Teacher's Note:
1. Absorption law: \( A(A+B) = A \).

Question 9: What is the output of the Boolean expression \( Y = A\bar{B} + AB \) when A = 1 and B = 0?
(a) 1
(b) 0
(c) both 1 and 0
(d) none of these
Show Answer & Explanation

Answer: (a) 1

Explanation:
1. \( Y = A(\bar{B} + B) = A = 1 \).
2. Direct substitution: \( 1 \cdot 1 + 1 \cdot 0 = 1 \).

Teacher's Note:
1. Simplify first: \( B + \bar{B} = 1 \).

Question 10: Inputs A, B go to an OR gate; its output and input C go to an AND gate whose output is Y. To get Y = 1, the input ABC should be:
(a) 101
(b) 100
(c) 110
(d) 010
Show Answer & Explanation

Answer: (a) 101

Explanation:
1. \( Y = (A+B) \cdot C \).
2. Y = 1 needs C = 1 and at least one of A, B equal to 1. Only 101 satisfies this.

Teacher's Note:
1. Check each option for C = 1 first.

Question 11: A NOR gate is followed by another NOR gate whose two inputs are joined together. The combination is logically equivalent to:
(a) an OR gate
(b) an AND gate
(c) a NOT gate
(d) a NAND gate
Show Answer & Explanation

Answer: (a) an OR gate

Explanation:
1. The first gate gives \( \overline{A+B} \).
2. The second acts as NOT, giving \( A+B \), which is OR.

Teacher's Note:
1. Joined inputs make a NOR gate act as an inverter.

Question 12: A two-input NAND gate is followed by a single-input NOR gate (i.e. a NOT gate). This circuit functions as:
(a) an AND gate
(b) an OR gate
(c) a NOT gate
(d) a NOR gate
Show Answer & Explanation

Answer: (a) an AND gate

Explanation:
1. NAND gives \( \overline{AB} \).
2. The following NOT restores AB, so it is an AND gate.

Teacher's Note:
1. Same as NAND followed by an inverter.

Question 13: In a circuit, A goes through a NOT gate to give \( \bar{A} \) and B goes through a NOT gate to give \( \bar{B} \). Then \( \bar{A} \) and B feed one AND gate and A and \( \bar{B} \) feed another; the two AND outputs feed an OR gate. This circuit performs the function of:
(a) AND gate
(b) NAND gate
(c) NOR gate
(d) XOR gate
Show Answer & Explanation

Answer: (d) XOR gate

Explanation:
1. \( Y = \bar{A}B + A\bar{B} \).
2. This is the XOR expression.

Teacher's Note:
1. XOR can be built from NOT, AND and OR.

Question 14: How many NOR gates are required to form a NAND gate?
(a) 1
(b) 3
(c) 2
(d) 4
Show Answer & Explanation

Answer: (d) 4

Explanation:
1. Two NOR gates joined as inverters give \( \bar{A} \) and \( \bar{B} \).
2. A third NOR on these gives \( \overline{\bar{A}+\bar{B}} = AB \), an AND gate.
3. A fourth NOR with joined inputs inverts AB to give NAND. Total = 4.

Teacher's Note:
1. Build AND first, then invert it.
2. NAND from NOR needs four gates, and NAND from NAND for NOT needs one.

Question 15: How many NAND gates are used to form an AND gate?
(a) 3
(b) 2
(c) 1
(d) 4
Show Answer & Explanation

Answer: (b) 2

Explanation:
1. One NAND gives \( \overline{AB} \).
2. A second NAND with joined inputs acts as an inverter to give AB.

Teacher's Note:
1. AND = NAND followed by NOT.

Question 16: The logic behind a NOR gate is that it gives:
(a) a high output when both inputs are high
(b) a high output when both inputs are low
(c) a low output when both inputs are low
(d) none of these
Show Answer & Explanation

Answer: (b) a high output when both inputs are low

Explanation:
1. NOR is 1 only when both inputs are 0.

Teacher's Note:
1. Compare with OR, which is 0 only for 00.

Question 17: Logic gates are the building blocks of a:
(a) abacus system
(b) analog system
(c) digital system
(d) none of these
Show Answer & Explanation

Answer: (c) digital system

Explanation:
1. Logic gates process binary signals 0 and 1.
2. They form the basis of digital systems.

Teacher's Note:
1. Digital circuits use discrete levels.

Question 18: Boolean algebra is essentially based on:
(a) logic
(b) truth
(c) numbers
(d) symbols
Show Answer & Explanation

Answer: (a) logic

Explanation:
1. Boolean algebra deals with logical variables taking values 0 and 1.

Teacher's Note:
1. It was introduced by George Boole to study logic.

Question 19: Out of the following, a universal gate is:
(a) NOT
(b) OR
(c) AND
(d) NAND
Show Answer & Explanation

Answer: (d) NAND

Explanation:
1. NAND (and NOR) can implement every other gate.

Teacher's Note:
1. Universal gates can build any logic circuit.

Question 20: Two NAND gates are connected in series, with both inputs of the second gate joined to the output of the first. The inputs of the first are A and B. This logic circuit is:
(a) NAND
(b) AND
(c) NOR
(d) OR
Show Answer & Explanation

Answer: (b) AND

Explanation:
1. The second NAND acts as an inverter, so the output is \( \overline{\overline{AB}} = AB \).
2. This is an AND gate.

Teacher's Note:
1. Two NAND gates in this pattern give AND.

Question 21: When a p-n diode is reverse biased:
(a) no current flows
(b) the depletion region is increased
(c) the depletion region is reduced
(d) the height of the potential barrier is reduced
Show Answer & Explanation

Answer: (b) the depletion region is increased

Explanation:
1. Reverse bias raises the barrier and widens the depletion region.
2. A tiny leakage current still flows, so option (a) is wrong.

Teacher's Note:
1. Forward bias reduces the width.
2. Reverse bias increases it.

Question 22: A NAND gate has its output joined to both inputs of a second NAND gate. The inputs of the first NAND gate are the two inputs of the circuit. The circuit represents the logical operation:
(a) AND
(b) NOT
(c) OR
(d) NOR
Show Answer & Explanation

Answer: (a) AND

Explanation:
1. The second gate acts as a NOT gate.
2. So the output is \( \overline{\overline{AB}} = AB \), the AND operation.

Teacher's Note:
1. NAND followed by NAND with joined inputs gives AND.

Question 23: An amplifier has a voltage gain \( A_V = 1000 \). The voltage gain in dB is:
(a) 30 dB
(b) 60 dB
(c) 3 dB
(d) 20 dB
Show Answer & Explanation

Answer: (b) 60 dB

Explanation:
1. Gain in dB = \( 20 \log_{10} A_V = 20 \log 1000 = 60 \) dB.

Teacher's Note:
1. Voltage gain uses 20 log, power gain uses 10 log.

Question 24: The minimum potential difference between the base and emitter required to switch a silicon transistor ON is approximately:
(a) 1 V
(b) 3 V
(c) 5 V
(d) 4.2 V
Show Answer & Explanation

Answer: (a) 1 V

Explanation:
1. A silicon base-emitter junction starts conducting at about 0.7 V.
2. Of the values given, 1 V is the closest.

Teacher's Note:
1. Si: about 0.7 V. Ge: about 0.3 V.

Question 25: A common emitter amplifier has a voltage gain of 50, an input impedance of 100 \( \Omega \) and an output impedance of 200 \( \Omega \). The power gain is:
(a) 100
(b) 500
(c) 1000
(d) 1250
Show Answer & Explanation

Answer: (d) 1250

Explanation:
1. Current gain = \( A_V \times R_{in}/R_{out} = 50 \times 100/200 = 25 \).
2. Power gain = 50 × 25 = 1250.

Teacher's Note:
1. Power gain is voltage gain times current gain.

Question 26: A p-n photodiode is made of a material with a band gap of 2.0 eV. The minimum frequency of radiation that can be absorbed is nearly:
(a) \( 1 \times 10^{14} \) Hz
(b) \( 20 \times 10^{14} \) Hz
(c) \( 10 \times 10^{14} \) Hz
(d) \( 5 \times 10^{14} \) Hz
Show Answer & Explanation

Answer: (d) \( 5 \times 10^{14} \) Hz

Explanation:
1. \( \nu = E/h = (2 \times 1.6 \times 10^{-19})/(6.63 \times 10^{-34}) \approx 4.8 \times 10^{14} \) Hz.
2. This is nearly \( 5 \times 10^{14} \) Hz.

Teacher's Note:
1. Photon energy must at least equal the band gap.

Question 27: The combination of a NOR gate, followed by a NAND gate with joined inputs, followed by a NOT gate is equivalent to:
(a) NOR gate
(b) OR gate
(c) AND gate
(d) NAND gate
Show Answer & Explanation

Answer: (a) NOR gate

Explanation:
1. The NAND gate with joined inputs acts as NOT.
2. Two NOT operations cancel, so the circuit equals the NOR gate.

Teacher's Note:
1. Count the inversions after the first gate.

Question 28:
Assertion (A): To be used as an amplifier, the transistor in the common emitter configuration is preferred to the common base configuration.
Reason (R): In the common emitter configuration, the signal is applied between emitter and base.
(a) Both A and R are true, and R is the correct explanation of A.
(b) Both A and R are true, but R is not the correct explanation of A.
(c) A is true, but R is false.
(d) A is false, but R is true.
Show Answer & Explanation

Answer: (b) Both A and R are true, but R is not the correct explanation of A.

Explanation:
1. CE gives high voltage, current and power gain.
2. The signal is applied between base and emitter, so R is true but is not the reason for A.

Teacher's Note:
1. Gain is the reason for preferring CE.

Question 29:
Assertion (A): In a solar cell it is essential that photogeneration of electrons and holes occurs in the depletion region.
Reason (R): The junction field separates the electron-hole pair effectively.
(a) Both A and R are true, and R is the correct explanation of A.
(b) Both A and R are true, but R is not the correct explanation of A.
(c) A is true, but R is false.
(d) A is false, but R is true.
Show Answer & Explanation

Answer: (a) Both A and R are true, and R is the correct explanation of A.

Explanation:
1. Pairs formed in the depletion region are quickly separated by the junction field.
2. That is why they contribute to the current.

Teacher's Note:
1. The field drives electrons to n and holes to p.

Question 30:
Assertion (A): In a transistor, the common emitter configuration is used to make a NOT gate.
Reason (R): In the common emitter configuration, the output voltage and input voltage have a 180 degree phase difference.
(a) Both A and R are true, and R is the correct explanation of A.
(b) Both A and R are true, but R is not the correct explanation of A.
(c) A is true, but R is false.
(d) A is false, but R is true.
Show Answer & Explanation

Answer: (a) Both A and R are true, and R is the correct explanation of A.

Explanation:
1. The CE circuit inverts the signal.
2. That inversion is the NOT operation, so R explains A.

Teacher's Note:
1. High input gives low output, and low input gives high output.

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Practice MCQs for JEE Physics Semiconductor Electronics

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